Abstract
Keywords
System on Chip, Image Processing, Retina, CMOS/APS Sensors
Abstract
The paper presents a general conclusion on the aptitude of CMOS retinas to become potential candidates for systems on chip, consequently to reach an algorithm-architecture-system adequacy. In this context, an application was selected making it possible to develop a conclusion on a partial integration of a system on chip. Hence the paper focuses on the VLSI compatibility of retinas, more particularly, of integrating image processing algorithms and their processors on the same sensor focal plane to provide a smart on chip vision system. The paper includes recommendations on system-level architecture and a design methodology for integrating image processing within a CMOS retina on a single chip. It highlights a compromise between versatility, parallelism, processing speed and resolution. Our solution aims to take also into account the algorithms response times while reducing energy consumption so as to increase the system performances for an intelligent vehicle application.